Configurable Advanced Touch-Screen LCD Video Evaluation Platform for Lattice FPGA Families

Lattice Semiconductor Corporation has announced the release of LCD-Pro, an advanced FPGA-based LCD video imaging and control solutions platform.
The LCD-Pro evaluation platform is based on the low-cost LatticeECP2
(TM) and LatticeXP2(TM) FPGA devices, and the UltiLogic family of graphics Intellectual Property (IP) Cores from Exor International. The LCD-Pro platform addresses a wide range of active matrix TFT displays from 2 inches to 23 inches, and enables rapid evaluation of advanced LCD video and touch-screen controller IP designed to accelerate time-to-market for manufacturers developing LCD video display and HMI (Human-Machine Interface) applications in automotive, consumer, white goods, building automation and industrial control markets.
Designed to provide comprehensive graphic processing functionality, the LCD-Pro platform incorporates a 2D graphics accelerator and can handle picture scaling and the cropping of real-time video. An I2C interface facilitates “plug-and-play” LCD connectivity while a backlight inverter provides ON/OFF and dimming control.
The LCD-Pro evaluation kit includes
- Carrier Board including 2x CVBS and 1x VGA Video Input Ports
- LatticeECP2-50 based FPGA module
- 7″ WVGA LCD Color Touch Display
- Color Video Camera
- 12 VDC Power Supply
- USB 2.0 Cable
- Adapter for Lattice JTAG Cable
- FPGA: LFE2-50E 5FN484C
- SPI Flash
- M25P32 – 4Mx8bit DDR Video Memory 64MB (32Mx16bit)
- 48MHz Oscillator
- JTAG port
- Analog circuits for A/D-D/A converters,
- Analog front end for Video Input,
- Universal LCD and Touch Screen connectors
For more information on the LCD-Pro evaluation kit, please contact us.
MachXO – Most Versatile Non-Volatile PLD for Low-Density Applications

The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Widely adopted in a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single-device.
Designed for a broad range of low density applications, the MachXO PLD family is used in a variety of end markets including Automotive, Communications, Consumer, Computing, Industrial and Medical.
For more information on the MachXO family of PLDs, or development tools to support your design requirements, please contact us.
Lowest Power SERDES-capable FPGA in the industry

The LatticeECP3 family is the third generation high value FPGA from Lattice Semiconductor, which offers the industry’s lowest power consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs.
Features include:
- Low-power 65nm process with 4-input look-up table (LUT) fabric
- Logic densities from 17K to 149K LUTs
- Upto 6.8Mbits of Embedded Block RAM (EBR)
- 2 DLLs per device, 2 to 10 PLLs per device
- High Speed embedded SERDES
- Multiply, accumulate, addition and subtraction
- High performance Adder Trees and MMAC functionality
- 54-bit Cascadable Arithmetic Logic Unit
- 24 to 320 multipliers (18×18)
- Advanced configuration options
- Flexible I/O buffers
- Wide range of Package & User I/O options
For more information on the LatticeECP3 family of FPGAs, or development tools to support your design requirements, please contact us.