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Monthly Archives: March 2013

Lattice MachXO2 PLD – Processor I/O Expansion with MachXO2 Cuts Cost and Reduces Power

Using the Lattice MachXO2 PLD’s hardened block functions you can easily add extra functions and more I/Os to a low pin count/low cost MCU based design. This reduces component cost, saves board space and saves power vs. using a higher pin count MCU. Also, the MachXO2 carries no overhead since it needs no configuration device.


Lattice MachXO2 PLD - Processor I/O

  • Discover how the hardened dual I2C, SPI, and Timer/Counter functions augment the flexible I/Os and logic blocks in the MachXO2 to efficiently support MCU-based designs.
  • See how a sensor monitoring solution example takes full advantage of the MachXO2 I/O expansion capabilities.
  • Watch the 7-minute video to better understand how the MachXO2 efficiently integrates system functionality and how easy it is to get started with free design tools, IP trials and reference designs.



Visit the “Lattice MachXO2 I/O Expansion” web page
to explore the full capabilities of the MachXO2 as an MCU I/O expansion device, or please
contact Allyanz todayfor more details.

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LatticeECP3 Delivers Rock Solid SERDES for Low Cost PCIe 2.0 Designs

The LatticeECP3 PCIe Solution is the first and only PCI Express 2.0 compliant low cost FPGA. With rock solid SERDES, an advanced PCI Express IP Core and a full-featured development kit the LatticeECP3 solution is ready to accelerate your next PCIe innovation, with an affordable price tag.

LatticeECP3

  • With up to 16 channels of low cost, low power SERDES, DSP slices, high-speed DDR3 memory interface capability and efficient FPGA fabric, the LatticeECP3 has all the features required for PCIe applications.
  • The Lattice PCI Express Endpoint IP Core has the advanced features needed to easily integrate PCIe 2.0 functionality with your design. Additionally, the Lattice Scatter Gather DMA IP Core can be used to further optimize transfer bandwidth.
  • The LatticeECP3 Versa Development Kit includes the full-featured evaluation board (with LatticeECP3 FPGA, Flash and DDR3 memory), free Lattice Diamond design environment, reference designs, demonstration systems and complete user documentation.

Visit the “LatticeECP3 PCIe Information Page” to learn how to simplify your low cost PCIe applications, or please contact Allyanz today for more details.

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Programmable Logic Devices Cuts Bill of Material Costs by up to 50%

Cut Bill of Material Costs by up to 50% for Board Power Management Functions
Programmable logic devices have been integrating digital functions to reduce cost, reduce board space and improve reliability for decades. Lattice’s programmable Power Manager II delivers these same capabilities, for both analog and digital functions, to dramatically cut bill of materials costs up to 50%, for board power management when compared to non-programmable implementations.


Board Power Management Functions

  • Discover how the Power Manager II can easily integrate even advanced functions, like hot-swap control, power sequencing and reset generation with fast shutdown times and over a wide voltage range.
  • See a design example that implements a hot-swap controller and manages the 1.2V, 2.5V and 3.3V board supply rails.
  • Watch the video to see how the Power Manager II solves common system challenges associated with 12V hot swap designs.

Visit the “How Swap Controller using Power Manager II” web page to explore the full capabilities of the Power Manager II for Hot Swap Designs, or please contact Allyanz today for more details.

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