The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Widely adopted in a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single-device.
Designed for a broad range of low density applications, the MachXO PLD family is used in a variety of end markets including Automotive, Communications, Consumer, Computing, Industrial and Medical.
For more information on the MachXO family of PLDs, or development tools to support your design requirements, please contact us.
The LatticeECP3 family is the third generation high value FPGA from Lattice Semiconductor, which offers the industry’s lowest power consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs.
- Low-power 65nm process with 4-input look-up table (LUT) fabric
- Logic densities from 17K to 149K LUTs
- Upto 6.8Mbits of Embedded Block RAM (EBR)
- 2 DLLs per device, 2 to 10 PLLs per device
- High Speed embedded SERDES
- Multiply, accumulate, addition and subtraction
- High performance Adder Trees and MMAC functionality
- 54-bit Cascadable Arithmetic Logic Unit
- 24 to 320 multipliers (18×18)
- Advanced configuration options
- Flexible I/O buffers
- Wide range of Package & User I/O options
For more information on the LatticeECP3 family of FPGAs, or development tools to support your design requirements, please contact us.