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Lattice Certus-NX Redefines Low Power, High I/O Count FPGAs

Looking for an FPGA that delivers greater I/O density and lower power in a significantly smaller package? Check out Lattice’s new Certus™-NX family of FPGAs. Leveraging the tremendous advantages of Lattice’s new Nexus platform – the industry’s first low power FPGA platform to use a 28-nm FD-SOI process technology – Certus-NX offers industrial and automotive designers best-in-class power savings, up to a 3x smaller form factor, higher reliability, and instant-on performance.

Lattice Certus-NX Redefines Low Power, High I/O Count FPGAs

And to help designers meet rapidly changing connectivity and performance needs, the Certus-NX adds PCIe and Ethernet chip-to-chip connectivity.

Features include:

  • Up to 39K logic cells, 2.9 Mb embedded memory, 56 18 x 18 multipliers, 192 programmable I/O, one lane of 5 Gbps PCIe, two lanes of 1.25 Gbps SGMII, two ADCs (each 12-bit, 1 MSPS).
  • Packages as small as 6×6 mm, and in ball-pitch options of 0.5 and 0.8 mm.
  • Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.
  • Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.
  • Instant-on configuration – I/O configures in 3 ms, and full-device as fast as 8 ms.

Additionally, Lattice released version 2.1 of the Radiant design software, which includes support for Certus-NX and SystemVerilog to make it easier than ever for developers to build applications based on the latest FPGA technology.

For more information, evaluation boards or samples please contact Allyanz.

MachXO – Most Versatile Non-Volatile PLD for Low-Density Applications

MachXO - Most Versatile Non-Volatile PLD for Low-Density Applications

The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. Widely adopted in a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single-device.

Designed for a broad range of low density applications, the MachXO PLD family is used in a variety of end markets including Automotive, Communications, Consumer, Computing, Industrial and Medical.

For more information on the MachXO family of PLDs, or development tools to support your design requirements, please contact us.

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Lowest Power SERDES-capable FPGA in the industry

Lowest Power SERDES-capable FPGA in the industryy

The LatticeECP3 family is the third generation high value FPGA from Lattice Semiconductor, which offers the industry’s lowest power consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs.

Features include:

  • Low-power 65nm process with 4-input look-up table (LUT) fabric
  • Logic densities from 17K to 149K LUTs
  • Upto 6.8Mbits of Embedded Block RAM (EBR)
  • 2 DLLs per device, 2 to 10 PLLs per device
  • High Speed embedded SERDES
  • Multiply, accumulate, addition and subtraction
  • High performance Adder Trees and MMAC functionality
  • 54-bit Cascadable Arithmetic Logic Unit
  • 24 to 320 multipliers (18×18)
  • Advanced configuration options
  • Flexible I/O buffers
  • Wide range of Package & User I/O options

For more information on the LatticeECP3 family of FPGAs, or development tools to support your design requirements, please contact us.

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